1. Field of the Invention
The present invention relates to a CMOS image sensor and method for manufacturing the same, and more particularly to a CMOS image sensor and method for manufacturing the same, in which active and field regions of the CMOS image sensor are not damaged by ion implantation.
2. Description of the Related Art
In general, an image sensor is a semiconductor device for converting an optical image into an electrical signal, and is generally classified into a CCD (Charge Coupled Device) and a CMOS (Complementary MOS) image sensor.
The CCD is a device in which charge carriers are stored and transferred under the situation that each MOS capacitor is closely disposed to each other, while the CMOS image sensor is a device employing a switching mode of forming MOS transistors as many as the number of pixels using CMOS technology, which makes use of controlling and signal processing circuits as a peripheral circuit, to detect outputs using the MOS transistors.
The CCD has various disadvantages, such as complicated drive mode, much power consumption, impossibility of realization of a signal processing circuit in a chip for the CCD due to many mask processes, and so on. Currently, in order to overcome these disadvantages, many studies are made of development of the CMOS image sensor using sub-micron CMOS manufacturing technology.
The CMOS image sensor obtains an image by forming a photodiode and a MOS transistor within a unit pixel to detect signals in a switching mode. As mentioned above, because the CMOS image sensor makes use of such CMOS manufacturing technology, the CMOS image sensor has little power consumption as well as a simple manufacturing process requiring about 20 masks, compared with the CCD manufacturing process requiring 30 to 40 masks. As a result, the CMOS image sensor can integrate a signal processing circuit into a single chip, so that it is possible to make a product compact, and thereby allowing for various applications.
Hereinafter, a description will be made regarding a construction of a conventional CMOS image sensor. FIGS. 1 and 2 are a circuit diagram and a layout diagram showing a structure of a unit pixel of the conventional CMOS image sensor. For the sake of reference, the number of transistors constituting the CMOS image sensor is three or more. However, for the sake of convenience of description, the CMOS image sensor with three transistors will be mainly described.
As shown in FIGS. 1 and 2, a unit pixel 100 of the CMOS image sensor comprises a photodiode 110 as a means for sensing light and three NMOS (N-channel Metal Oxide Semiconductor) transistors. Among the three transistors, one is a reset transistor (Rx) 120, which functions not only to transfer optical charges generated from the photodiode 110 but also to discharge charges so as to detect signals, another is a drive transistor (Dx) 130, which functions as a source follower, and the other is a select transistor (Sx) 140, which performs switching and addressing functions.
Meanwhile, in the CMOS image sensor of the unit pixel, the photodiode 110 is designed to function as a source of the reset transistor (Rx) 120 in order to facilitate movement of the charges. To this end, in the course of manufacturing the image sensor of the unit pixel, a process of implanting low- or high-concentration dopant ions into a location including a part of the photodiode 110 is used as shown in FIG. 2. The manufacturing process will be described with reference to a cross-section taken along line A-A′ of FIG. 2. For the sake of reference, a solid line of FIG. 2 indicates an active region 160.
First, as shown in FIG. 3a, a gate insulating layer 122 and a gate electrode 123 are sequentially formed on a p-type semiconductor substrate 101, on which an isolating layer 121 is completely formed using a shallow trench isolation (STI) and the like. Here, even though not shown, a p-type epitaxial layer may be previously formed within the p-type substrate. Subsequently, a photosensitive layer is applied on the front surface of the substrate, and then a pattern for the photosensitive layer, which defines a region of the photodiode, is formed using a photolithography process. Here, the photosensitive layer pattern does not expose the gate electrode.
In this state, low-concentration dopant ions, for example n-type dopant ions, are implanted into the substrate, so that there is formed a low-concentration dopant region n− having a predetermined depth in the substrate.
Next, as shown in FIG. 3b, another photosensitive layer pattern which does not expose the low-concentration dopant region is formed, and then another low-concentration dopant region for an LDD structure is formed in a drain region of the electrode using the another photosensitive layer pattern as an ion implantation mask.
Subsequently, as shown in FIG. 3c, a spacer is formed on a side wall of the gate electrode, and then a p-type dopant region p0 is formed on the n-type dopant region n−. Thereby, a process of forming the photodiode is completed. When the photodiode is finished, high-concentration dopant ions are selectively implanted to form a high-concentration dopant region n+ in the drain region of the gate electrode. As a result, the process associated with the cross-section taken along line A-A′ of FIG. 2 is terminated.
According to the conventional method for manufacturing the CMOS image sensor, during implantation of low-concentration dopant ions in the photodiode region, the implantation is performed throughout the active region as well as the isolating layer. In this case, because of an interface between the isolating layer and the active region, defects may be generated in the substrate by ions implanted into the interface.
These defects caused by ion implantation generate carriers of the charges or holes and provide locations at which the charges and holes may be rejoined, thus generating or increasing a leakage current of the photodiode. In other words, a dark current (i.e., a phenomenon that electrons move to a floating diffusion region in the photodiode while no light is present) is generated. The dark current is mainly incurred form various defects distributed around the silicon surface, at the interface between the isolating layer and the p-type dopant region p0, at the interface between the isolating layer and the low-concentration dopant region n−, at the interface between the p-type dopant region p0 and the low-concentration dopant region n−, at the p region or at the low-concentration dopant region n− or from a dangling bond. The dark current adversely affects low illumination characteristics of the CMOS image sensor.
Further, when an ion implantation mask is formed on the isolating layer from the photosensitive layer pattern in order to prevent dopant ions from being doped into the isolating layer, the I-line wavelength used as an exposure source for patterning the photosensitive layer may cause minute variations in the pattern profile, so that it is difficult to exactly align the isolating layer with the photosensitive layer pattern. For this reason, when an image sensor having repeated unit pixels is manufactured, the image sensor may have a reproducibility problem in the unit pixels not having exactly the same characteristics.
It is proposed from U.S. Pat. No. 6,462,365 that an isolating layer and a transfer gate are formed at a location corresponding to a photodiode region in order to restrict a dark current generated by a damaged photodiode. In addition, various resolutions for minimizing the dark current have been proposed. However, effective solutions related to defects generated by ion implantation at the interface between the isolating layer and the active region are generally not widely known or practiced.